1. Field of the Invention
The present invention relates to semiconductor fabrication, in particularly to a method for fabricating a fin-shaped semiconductor structure.
2. Description of the Related Art
The escalating demands for high density and performance associated with ultra large scale integrated semiconductor devices require design features, such as gate lengths, to be below 100 nanometers (nm), high reliability and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methods.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are, therefore, being explored to improve FET performance and allow further device scaling.
A FinFET is a recent structure developed that exhibits good short channel behavior, including a channel formed in a vertical fin-shaped semiconductor structure. The FinFET may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs, however, fabrication of the vertical fin-shaped semiconductor structure of the FinFET, is problematic since an end point during an etching process for forming the vertical fin-shaped semiconductor structure cannot be determined by conventional interferometer end point (IEP) detection or optical emission spectroscopy (OES) detection. This is due to the non-planar surface configuration of the formed fin-shaped semiconductor structure such that a thickness and a shape of the vertical fin-shaped semiconductor structure cannot be precisely controlled by the above described end point detection methods.